The following disclosure relates to electrical circuits and signal processing.
High speed transmitters (e.g., a 10 GHz wireline transmitter) typically include a phase locked loop (PLL) clock divider for generating multiple clock signals, each having a different phase.
FIG. 1 shows one example of a conventional PLL clock divider 100. Phase interpolator 100 includes a voltage controlled oscillator (VCO) 102 and clock dividers 104–110. In the example shown, VCO 102 produces a 10 GHz clock signal that is respectively divided into a 5 GHz clock signal, a 2.5 GHz clock signal, a 1.25 GHz clock signal, and a 625 MHz clock signal by clock dividers 104–110. Due to an inherent delay associated with each of clock dividers 104–110, the 5 GHz clock signal is typically skewed (or delayed) with respect to the 10 GHz clock signal as represented by delay td1 in FIG. 1. Similar delays td2, td3, td4 are associated with the 2.5 GHz clock signal, the 1.25 GHz clock signal, and the 625 MHz clock signal.
In a high speed transmitter, the multiple clock signals generated by a PLL clock divider (e.g., PLL clock divider 100) can be used to combine parallel data streams into a serial data stream through a serializer circuit. FIG. 2 shows a conventional serializer circuit 200 including a four stage multiplexer 202 and a retiming circuit 204. As shown in FIG. 2, (16) low speed (e.g., 625 MHz) streams of data—i.e., data streams 1–16—are combined through multiplexer 202 to generate a high speed (e.g., 10 GHz) data stream. The clock signals generated by PLL clock divider 100 are respectively used to clock each stage of multiplexer 200 and to retime a final data stream through retiming circuit 204. Data streams 1–16 are typically delayed by each stage of multiplexer 202 as represented by delays td5–td8. Each delay td5–td8 is substantially equal to (1) clock-to-Q delay. A clock-to-Q delay represents an amount of time from assertion of a multiplexer clock until the multiplexer output becomes valid.
As a result of clock signal delays td1–td4 and data stream delays td5–td8, clock signals and data streams may lose alignment as lower speed data streams are combined into data streams of higher rate. Such loss of alignment may adversely affect the integrity and yield of data being transmitted from a high speed transmitter.